This invention relates generally to a memory apparatus for a personal computer and and more particularly to a memory apparatus comprising a plurality of commercially available semiconductor memory units which are configured to provide a designated memory size or capacity.
A memory apparatus having a 16-bit data bus width can be comprised of a plurality of semiconductor elements or units of identical structure. For example, a 256K (Kwords).times.16 bit (512 Kbytes) memory apparatus can be comprised of four 256K.times.4 bit semiconductor memory units, a 512K.times.16 bit (1 Mbyte) memory apparatus can be comprised of 8 such memory units, a 768K.times.16 bits (1.5 Mbytes) memory apparatus can be comprised of 12 such memory units, and a 1024K.times.16 bit (2 Mbytes) memory apparatus can be comprised of 16 such memory units. In these cases, each time the number of memory units is increased by four, the memory capacity is increased in units of 512 Kbytes.
For example, when sixteen 1 Meg (Mwords).times.1 bit semiconductor memory units are employed, a memory apparatus having a memory capacity of 2 Mbytes can be achieved. In this case, each time the number of semiconductor memory units is increased by 16, the memory capacity is increased in units of 2 Mbytes.
In the forgoing manner, a memory apparatus can be designed as a plurality of semiconductor memory units all of the same type. Typical memory apparatus are summarized in Table 1 below.
TABLE 1 ______________________________________ Data Type of Required Number Capacity of Bus Memory of Memory Memory Width Element Used Elements Apparatus ______________________________________ 32 Bits 128 Kwords .times. Integer Multiple Integer Multiple 8 Bits of 4 of 512 Kbytes 32 Bits 256 Kwords .times. Integer Multiple Integer Multiple 4 Bits of 8 of 1 Mbyte 32 Bits 1 Mword .times. Integer Multiple Integer Multiple 1 Bit of 32 of 4 Mbytes 32 Bits 512 Kwords .times. Integer Multiple Integer Multiple 8 Bits of 4 of 2 Mbytes 32 Bits 1 Mword .times. Integer Multiple Integer Multiple 4 Bits of 8 of 4 Mbytes 32 Bits 4 Mwords .times. Integer Multiple Integer Multiple 1 Bit of 32 of 16 Mbytes 16 Bits 128 Kwords .times. Integer Multiple Integer Multiple 8 Bits of 2 of 256 Kbytes 16 Bits 256 Kwords .times. Integer Multiple Integer Multiple 4 Bits of 4 of 512 Kbytes 16 Bits 1 Mword .times. Integer Multiple Integer Multiple 1 Bit of 16 of 2 Mbytes 16 Bits 512 Kwords .times. Integer Multiple Integer Multiple 8 Bits of 2 of 1 Mbyte 16 Bits 1 Mword .times. Integer Multiple Integer Multiple 4 Bits of 4 of 2 Mbytes 16 Bits 4 Mwords .times. Integer Multiple Integer Multiple 1 Bit of 16 of 8 Mbytes 8 Bits 128 Kwords .times. Integer Multiple Integer Multiple 8 Bits of 1 of 128 Kbytes 8 Bits 256 Kwords .times. Integer Multiple Integer Multiple 4 Bits of 2 of 256 Kbytes 8 Bits 1 Mword .times. Integer Multiple Integer Multiple 1 Bit of 8 of 1 Mbyte ______________________________________
However, as can be understood from the above description and the content of Table 1, when a memory apparatus is constituted by using a plurality of semiconductor memory units of the same type, the capacity of the memory apparatus is limited to an integer multiple of a minimum capacity in accordance with its data bus width and combinations of semiconductor memory units employed.
For example, when a memory apparatus for a microprocessor having a 16-bit data bus width is to be formed by 256K.times.4 bit memory units, if four memory units are employed, a 512-Kbytes memory apparatus can be arranged. However, since the next largest memory capacity is 1 Mbyte using eight memory units, an intermediate memory capacity of 640 Kbytes cannot be obtained.
At present, a value "640 Kbytes" is a very significant memory size. More specifically, as an operating system for existing personal computers, the disk operating system (DOS) is most widely used and DOS requires 640 Kbytes for the standard main memory. Therefore, a memory apparatus having a memory capacity of exactly 640 Kbytes is required. In practice, almost all presently commercially available personal computers are equipped with 640-Kbyte main memories. The 640-Kbyte memory apparatus, however, cannot be constituted by a combination of semiconductor memory units of the same type but is formed by combining two or more types of semiconductor memory units.
More particularly, in order to comprise a 640-Kbyte memory apparatus, sixteen 256K.times.1 bit, 256-Kbit DRAMs (hereinafter referred to as 256K.times.1, 256K DRAMs) and four 64K.times.4 bit, 256-Kbit DRAMs (hereinafter referred to as 64K.times.4, 256K DRAMs) are employed, as illustrated in FIG. 2. This is because 256K DRAMs are most advantageous in terms of cost and are of ample supply. In FIG. 2, the 256K.times.1, 256K DRAMs are indicated by reference numeral 100 and the 64K.times.4,256K DRAMs are indicated by reference numeral 101. It is to be noted that FIG. 2 only illustrates connections of data terminals of the DRAMs and does not particularly show address and control terminals, such as, for example, RAS, CAS, and WE signals. In this connection, the connections of the data terminals are important relative to the understanding of the present invention, but the connections of other terminals relative to these DRAMs are not important to the understanding and employment of this invention and are already readily understood by those who are skilled in the art relative to the design of personal computers. Therefore, description and reference to these other DRAM terminal connections are not necessary to the description of this invention and are omitted.
In FIG. 2, a 512-Kbyte memory (256K.times.16 bits) is comprised of sixteen 256K.times.1 DRAMs, a 128-Kbyte memory (64K.times.16 bits) is comprised of four 64K.times.4 DRAMs and their data bus lines (MD15 to MD0) are connected in parallel with each other to constitute a 640-Kbyte memory apparatus (320K.times.16 bits). The 16-bit data bus (MD15 to MD0) of the memory is connected to a data bus of a microprocessor having a 16-bit data bus width through a buffer (not shown).
It is to be noted that reference numerals 105 and 106 denote 256K.times.1 parity-bit DRAMs and 107 and 108, 64K.times.1 parity-bit DRAMs. The DRAMs 105 and 107 correspond to upper 8 bits (odd-numbered byte), and the DRAMs 106 and 108 correspond to lower 8 bits (even-numbered byte). For parity bits, four 1-bit output DRAMs 105 to 108 are employed. However, the parity-bit DRAM may also be comprised of a one 4-bit output DRAM. Since parity bits of the memory apparatus are not directly related to the present invention, further reference thereto is not necessary.
In FIG. 2, a total of twenty 256K DRAMs are employed. With the progression of semiconductor technology, there is a trend to shift from the use of 256K DRAMs to the use of 1M DRAMs. With this trend, manufacturers of personal computers now frequently employ 1M DRAMs. In this connection, a 640-Kbyte memory apparatus comprises a total of eight DRAMs, i.e., four 256K.times.4 bit, 1-Mbit DRAMs (hereinafter referred to as 256K.times.4, 1M DRAMs) and four 64K.times.4, 256K DRAMs, as shown in FIG. 3. More particularly, four 64K.times.4, 256K DRAMs form a 128-Kbyte memory (64K.times.16 bit) and four 256K.times.4, 1M DRAMs 102 form a 512-Kbyte memory (256K.times.16 bit). These memories are combined to constitute a 640-Kbyte (320K.times.16 bit) memory apparatus. A 16-bit data bus (MD 15 to MD 0) of the memory is connected via a buffer to the data bus of the microprocessor.
In the memory apparatus shown in FIG. 3, the sixteen 256K.times.1, 256K DRAMs shown in FIG. 2 are replaced with four 256K.times.4, 1M DRAMs. However, the four 64K.times.4, 256K DRAMs in FIG. 2 cannot be replaced with a 1M DRAM. If these DRAMs are replaced with a 1M DRAM, a 64K.times.16, 1-Mbit DRAM is necessary but such a DRAM is not commercially available. If such a DRAM were available, its cost would be comparatively higher since it would be a special or hybrid type and the number of pin outputs would be large resulting in a large IC package. Since 16 data bus lines would extend from a single package, the amount of noise would be increased and, as a result, stable operation would not be assured. Therefore, nearly all 640-Kbyte memory apparatus for personal computers have the configuration as shown in FIG. 2.
Thus, when a memory apparatus having a 16-bit data bus width is comprised of, e.g., 256K.times.4 memory units by a conventional method of constituting a memory apparatus, a 512-Kbyte or 1-Mbyte apparatus can be formed, but a 640-Kbyte apparatus is not possible. In order to provide a 640-Kbyte memory apparatus by the conventional approach, four 64K.times.4, 256K DRAMs are necessary in addition to four 256K.times.4, 1M DRAMs.
As previously indicated, however, manufacturers of semiconductor memory devices have recently shifted emphasis to the manufacture and sale of 1M DRAMs with an accompanying trend toward the decrease of production quantities of 256K DRAMs. In fact, the production of 256K DRAMs may be terminated by many manufactures in the near future. More particularly, semiconductor memory units of one type tend to be intensively manufactured according to current needs and demand. For this reason, semiconductor memory units other than those which are currently, intensively manufactured cannot be supplied in large quantities, which results in high cost. Therefore, it may become difficult to obtain a sufficient supply of production quantity, high quality 256K DRAMs which will directly affect the production quantities of personal computers. In addition, the cost of 256K DRAMs will also increased. Thus, an important goal for the manufacturers of personal computers in the future is to develop personal computers which do not require 256K DRAMs for memory.
If a memory apparatus can be formed by employing only semiconductor memory units of a single type and capacity, which are currently mass-produced in the largest quantities, a memory apparatus and a personal computer adopting the memory apparatus can be supported at low cost without restricting production quantities of the personal computer.
It is an object of the present invention to provide a memory apparatus which employs semiconductor memory units of one type while also providing a high degree of freedom relative to its total memory capacity, i.e., providing a flexibility wherein its total memory capacity can be formed in relatively small units.